
`define PSRAM_SIMPLE_TRAIN
module apb2_fp_slave
(
	output[31:0] prdata_fp ,
	
	input pclk        ,
	input rstn     ,
	input psel_fp     ,
	input penable_fp  ,
	input pwrite_fp   ,
	input[31:0] pwdata_fp   ,
	input[7:0] paddr_fp    ,

	output ps_ck,
	output ps_dir,
	output ps_en0,
	output ps_en1,
	output [2:0] pssel,
	
	output reg[31:0] func_test,	

 //**********************************************************//
//psram ctrl 
    output reg[31:0]  psram_ctrl,
	output[15:0] psram_wdata_o0,
	output[15:0] psram_wdata_o1,
	output reg[31:0] psram_addr,
	input[15:0] psram_rdata0,
	input[15:0] psram_rdata1,


	input psram_rd_val0,
	input psram_rd_val1,
	input psram_clk,
	input psram_rd_clk,
    input psram_data_load0,
    input psram_data_load1,
    input psram_finish,
    input ltcy_mode0,
    input ltcy_mode1,
	
 //**********************************************************//
 //rgmii_ctrl
 
    output rgmii_tx_start,
    output rgmii_rx_start,
	output rgmii_test_en,
    output phy_rstn,
    output rgmii_pll_rst,
    output[15:0] rgmii_tx_num,
    input[31:0] rgmii_tx_pkt_cnt,
    input rgmii_tx_finish,
	
	input mdio_sys_clk,
 	output op_sel0,//0 :wr, 1: rd
	output[4:0] phy_addr0,
	output[4:0] phy_reg0,
	output[15:0] dset0,
	output req0,
	input[15:0] dget0,
	input rd_ack0,
	
	output op_sel1,//0 :wr, 1: rd
	output[4:0] phy_addr1,
	output[4:0] phy_reg1,
	output[15:0] dset1,
	output req1,
	input[15:0] dget1,
	input rd_ack1,
	input phy_pwr_on_rdy,
	
 //**********************************************************//
//sram ctrl 
    input sram_capt_done0,
    input sram_capt_done1,
    input[31:0] misc_fifo_din,
    output  misc_fifo_rd,
    output  misc_fifo_rstn,



	output[9:0] test
	
	
);


wire slave_sel;
wire slave_wr;
wire slave_rd;
wire[7:0] slave_addr;

reg[31:0] prdata_fp_s;
reg ps_en1_s;


wire psram_wr;
wire psram_wr_en;
reg psram_w_f;
wire[7:0] psram_rdata_mcu;
wire[7:0] psram_rdata_mcu1;
wire psram_rd_en;
reg psram_rd_en_f;
reg psram_rd_en_s;
reg psram_finish_mcu_f;
reg psram_finish_mcu_s;
wire psram_fifo_rstn;
reg ps_en_s;

reg[2:0] ltcy_s0;
reg[2:0] ltcy_s1;
reg ltcy_det0;
reg ltcy_det1;
wire ltcy_clr;
reg[7:0] psram_ltcy_set;
wire bta_fifo_wr;
reg bta_fifo_s;
wire bta_fifo_wr_en;
reg[5:0] bta_addr;

reg psram_rd_val0_s;
wire psram_rd_val0_r;
reg psram_rd_val1_s;
wire psram_rd_val1_r;
reg[15:0] psram_rdata0_s;
reg[15:0] psram_rdata1_s;
wire fifo_rstn;
reg[1:0] part_req_get_s;
wire part_req_get_r;
reg part_req_get_mcu;
wire part_req_clr_mcu;
reg[7:0] mipi_part_ctrl;

reg[15:0] psram_rdata0_t;
reg[15:0] psram_rdata1_t;

wire[15:0] psram_rdata0_d;
wire[15:0] psram_rdata1_d;


wire psram_rfifo_en;
reg psram_rfifo_en_f;
reg psram_rfifo_en_s;

wire psram_wfifo_en;
reg psram_wfifo_en_f;
reg psram_wfifo_en_s;

wire psram_wfifo_rstn;
wire psram_rfifo_rstn;
wire[31:0] sram_status;

reg[1:0] sram_capt_done_s;

reg rd_ack0_f;
reg rd_ack1_f;
reg[15:0] dget0_s;
reg[15:0] dget1_s;
reg[31:0] mdio_ctrl0_s;
reg[31:0] mdio_ctrl1_s;
reg misc_fifo_rd_f;
reg phy_pwr_on_rdy_s;
reg rgmii_tx_finish_s;
reg[31:0] misc_fifo_din_s;

reg[31:0] rgmii_tx_pkt_cnt_f;
reg[31:0] rgmii_tx_pkt_cnt_s;
//***************************************************************//
//***************************************************************//
//***************************************************************//
//apb reg addr
	
// reg[31:0] func_test; // 0x5180_0000 for mcu

reg[31:0] pll_set_reg; // 0x5180_0004 for mcu

// output reg[31:0]  psram_ctrl,// 0x5180_0008 for mcu

						//psram ctrl rstn=psram_ctrl[31]; 
						//psram fifo rd pulse=psram_ctrl[10]; 
						//psram fifo wr pulse=psram_ctrl[9]; 
						//psram_ctrl_sel=psram_ctrl[8]; 0 : mcu , 1: fp
						//ltcy_clr=psram_ctrl[7];
						//psram_rfifo_rstn=psram_ctrl[6];
						//	psram_ctrl[5] psram rstn
						//	psram_ctrl[4] init mode
						
						//	psram_ctrl[2]  psram wr fifo rstn
						//	psram_ctrl[1]  rd
						//	psram_ctrl[0]  wr


reg[31:0] psram_wdata;// 0x5180_000c for mcu
// output reg[31:0] psram_addr,// 0x5180_0010 for mcu
wire[31:0] psram_status;// 0x5180_0014 for mcu

//sram_status   // 0x5180_0018
reg[31:0] rgmii_ctrl;// 0x5180_001c
reg[31:0] mdio_ctrl0;// 0x5180_0020
reg[31:0] mdio_ctrl1;// 0x5180_0024
reg[31:0] misc_fifo_ctrl;// 0x5180_0028
// reg[31:0] misc_fifo_din;// 0x5180_002c

assign psram_status={28'd0,
					1'b0,ltcy_det1,ltcy_det0,psram_finish_mcu_s};		
//****************************************************************//
//****************************************************************//
//****************************************************************//

//****************************************************************//
assign test[0]=psel_fp;
assign test[1]=pwdata_fp==32'h600800;
assign test[2]=slave_addr==3;
assign test[3]=slave_addr==4;
assign test[4]=psram_wdata[15:0]==16'h9f14;
assign test[5]=pwrite_fp;
assign test[6]=psram_addr==32'h600800;
assign test[7]=psram_addr==32'h600801;


//****************************************************************//
//apb 
assign slave_sel=psel_fp;
assign slave_wr=slave_sel&pwrite_fp;
assign slave_rd=slave_sel&(!pwrite_fp);
assign slave_addr=paddr_fp[7:0];   //assign paddr_fp  = glb_clear_b_d16_brg ? paddr_fp_gated[9:2] :  8'h0 ;

//****************************************************************//
//apb wr

always@(posedge pclk or negedge rstn)
begin
    if(!rstn)
		begin
			func_test <=32'd0;			
			pll_set_reg <=32'd0;
			psram_wdata<=32'h0;			
			psram_ctrl <=32'b0;
			psram_addr <=32'b0;
			rgmii_ctrl <=32'h2;
			mdio_ctrl0 <=32'b0;
			mdio_ctrl1 <=32'b0;
			misc_fifo_ctrl<=32'b0;
		end
	else if(slave_wr)
	begin
		case (slave_addr)
			8'h0: func_test<=pwdata_fp;
			8'h1: pll_set_reg<=pwdata_fp;
			8'h2: psram_ctrl<=pwdata_fp;
			8'h3: psram_wdata<=pwdata_fp;
			8'h4: psram_addr<=pwdata_fp;
			8'h7: rgmii_ctrl<=pwdata_fp;
			8'h8: mdio_ctrl0<=pwdata_fp;
			8'h9: mdio_ctrl1<=pwdata_fp;
			8'ha: misc_fifo_ctrl<=pwdata_fp;
		endcase
	end
end


//****************************************************************//
//apb rd
always@(posedge pclk or negedge rstn)
begin
    if(!rstn)
		begin
			prdata_fp_s <=32'd0;
		end
	else if(slave_rd)
	begin
		case (slave_addr)
			8'h0: prdata_fp_s <=func_test;
			8'h1: prdata_fp_s <=pll_set_reg;
			8'h2: prdata_fp_s<=psram_ctrl;
			8'h3: prdata_fp_s<={psram_rdata1_d,psram_rdata0_d};
			8'h4: prdata_fp_s<=psram_addr;
			8'h5: prdata_fp_s<=psram_status;
			8'h6: prdata_fp_s<=sram_status;
			8'h7: prdata_fp_s<=rgmii_ctrl;
		    8'h8: prdata_fp_s<={rgmii_tx_finish_s,phy_pwr_on_rdy_s,rd_ack0_f, dget0_s};
			8'h9: prdata_fp_s<={rd_ack1_f, dget1_s};
			8'ha: prdata_fp_s<=misc_fifo_ctrl;
			8'hb: prdata_fp_s<=misc_fifo_din_s;
			8'hc: prdata_fp_s<=rgmii_tx_pkt_cnt_s;
			default: prdata_fp_s<=32'h33333333;
		endcase
	end
end

assign prdata_fp=prdata_fp_s;

//****************************************************************//
//****************************************************************//
//****************************************************************//
//rgmii&phy
assign rgmii_tx_start=rgmii_ctrl[0];
assign rgmii_rx_start=rgmii_ctrl[3];
assign rgmii_test_en=rgmii_ctrl[4];
assign phy_rstn=rgmii_ctrl[1];
assign rgmii_pll_rst=rgmii_ctrl[2];
assign rgmii_tx_num=rgmii_ctrl[31:16];


always @(posedge pclk or negedge rstn) begin
    if(!rstn) begin
        rgmii_tx_pkt_cnt_f <=0;
        rgmii_tx_pkt_cnt_s <=0;
	end
    else begin
        rgmii_tx_pkt_cnt_f <= rgmii_tx_pkt_cnt;
        rgmii_tx_pkt_cnt_s <= rgmii_tx_pkt_cnt_f;
	end
end



always @(posedge pclk or negedge rstn) begin
    if(!rstn) begin
        rgmii_tx_finish_s <= 1'b0;
	end
    else begin
        rgmii_tx_finish_s <= rgmii_tx_finish;
	end
end


always @(posedge pclk or negedge rstn) begin
    if(!rstn) begin
        phy_pwr_on_rdy_s <= 1'b0;
	end
    else begin
        phy_pwr_on_rdy_s <= phy_pwr_on_rdy;
	end
end


always @(posedge pclk or negedge rstn) begin
    if(!rstn) begin
        rd_ack0_f <= 1'b0;
	end
    else begin
        rd_ack0_f <= rd_ack0;
	end
end

always @(posedge pclk or negedge rstn) begin
    if(!rstn) begin
        dget0_s <= 16'b0;
	end
    else begin
        dget0_s <= dget0;
	end
end



always @(posedge mdio_sys_clk or negedge rstn) begin
    if(!rstn)
        mdio_ctrl0_s <= 32'b0;
    else
        mdio_ctrl0_s <=mdio_ctrl0;
end


assign dset0=mdio_ctrl0_s[15:0];
assign phy_addr0=mdio_ctrl0_s[20:16];
assign phy_reg0=mdio_ctrl0_s[25:21];
assign op_sel0=mdio_ctrl0_s[26];
assign req0=mdio_ctrl0_s[31];


//****************************************************************//

always @(posedge mdio_sys_clk or negedge rstn) begin
    if(!rstn)
        mdio_ctrl1_s <= 32'b0;
    else
        mdio_ctrl1_s <=mdio_ctrl1;
end
always @(posedge pclk or negedge rstn) begin
    if(!rstn) begin
        rd_ack1_f <= 1'b0;
	end
    else begin
        rd_ack1_f <= rd_ack1;
	end
end

always @(posedge pclk or negedge rstn) begin
    if(!rstn) begin
        dget1_s <= 16'b0;
	end
    else begin
        dget1_s <= dget1;
	end
end

assign dset1=mdio_ctrl1_s[15:0];
assign phy_addr1=mdio_ctrl1_s[20:16];
assign phy_reg1=mdio_ctrl1_s[25:21];
assign op_sel1=mdio_ctrl1_s[26];
assign req1=mdio_ctrl1_s[31];

	
	
	
//****************************************************************//
//****************************************************************//
//****************************************************************//
//misc fifo


always @(posedge pclk or negedge rstn) begin
    if(!rstn)
        misc_fifo_din_s <= 32'b0;
    else
        misc_fifo_din_s <= misc_fifo_din;
end


always @(posedge pclk or negedge rstn) begin
    if(!rstn)
        misc_fifo_rd_f <= 1'b0;
    else
        misc_fifo_rd_f <= misc_fifo_ctrl[0];
end

assign misc_fifo_rd=misc_fifo_ctrl[0]&(!misc_fifo_rd_f);
assign misc_fifo_rstn=misc_fifo_ctrl[1];

//****************************************************************//
//****************************************************************//
//****************************************************************//


always @(posedge pclk or negedge rstn) begin
    if(!rstn)
        sram_capt_done_s <= 2'b0;
    else
        sram_capt_done_s <= {sram_capt_done1, sram_capt_done0};
end

assign sram_status={30'h123456, sram_capt_done_s};


//****************************************************************//
//****************************************************************//
//****************************************************************//
//pll ctrl
always @(posedge pclk or negedge rstn) begin
    if(!rstn)
        ps_en_s <= 1'b0;
    else
        ps_en_s <= pll_set_reg[7];
end

always @(posedge pclk or negedge rstn) begin
    if(!rstn)
        ps_en1_s <= 1'b0;
    else
        ps_en1_s <= pll_set_reg[8];
end

assign ps_ck=pclk;
assign ps_dir=pll_set_reg[6];
assign ps_en0=pll_set_reg[7]&(!ps_en_s);
assign ps_en1=pll_set_reg[8]&(!ps_en1_s);
assign pssel= pll_set_reg[2:0];


//****************************************************************//
//***************************************************************//
//***************************************************************//
//psram 

always @(posedge pclk or negedge rstn)
 begin
   if (!rstn) begin
		 psram_finish_mcu_f<=1'b0;
		 psram_finish_mcu_s<=1'b0;
	 end
	 else begin
		 psram_finish_mcu_f<=psram_finish;
		 psram_finish_mcu_s<=psram_finish_mcu_f;
	 end
 end


//***************************************************************//
assign ltcy_clr=psram_ctrl[7];

always @(posedge pclk or negedge rstn) begin
    if(!rstn)
        ltcy_s0 <= 3'b0;
    else
        ltcy_s0 <={ltcy_s0[1:0],ltcy_mode0};
end

always @(posedge pclk or negedge rstn) begin
    if(!rstn)
        ltcy_det0 <= 1'b0;
    else if(ltcy_s0[2])
        ltcy_det0 <= 1'b1;
	else if(ltcy_clr)
		ltcy_det0 <= 1'b0;
end

always @(posedge pclk or negedge rstn) begin
    if(!rstn)
        ltcy_s1 <= 3'b0;
    else
        ltcy_s1<={ltcy_s1[1:0],ltcy_mode1};
end

always @(posedge pclk or negedge rstn) begin
    if(!rstn)
        ltcy_det1 <= 1'b0;
    else if(ltcy_s1[2])
        ltcy_det1 <= 1'b1;
	else if(ltcy_clr)
		ltcy_det1 <= 1'b0;
end

//*****************************************************************//

`ifdef PSRAM_SIMPLE_TRAIN 

always @(posedge pclk)
 begin
   psram_rdata0_t<=psram_rdata0_s;
 end
 
always @(posedge pclk)
 begin
   psram_rdata1_t<=psram_rdata1_s;
 end
 
assign psram_rdata0_d=psram_rdata0_t;
assign psram_rdata1_d=psram_rdata1_t;

//*****************************************************************//
reg[15:0] psram_rd_val0_get;

always @ (posedge psram_clk or negedge rstn) begin
	if (!rstn) begin
		psram_rd_val0_s<=1'b0;
	end
	else begin
		psram_rd_val0_s<=psram_rd_val0;
	end
end 


always @ (posedge psram_clk or negedge rstn) begin
	if (!rstn) begin
		psram_rd_val0_get<=16'b0;
	end
	else begin
		psram_rd_val0_get<={psram_rd_val0_get[14:0],psram_rd_val0_r};
	end
end 


reg psram_rd_sel;
always @ (posedge psram_clk or negedge rstn) begin
	if (!rstn) begin
		psram_rd_sel<=1'b0;
	end
	else 
		psram_rd_sel<=psram_ctrl[9] ;
	
end 


assign psram_rd_val0_r = psram_rd_val0&(!psram_rd_val0_s);

always @ (posedge psram_clk or negedge rstn) begin
	if (!rstn) begin
		psram_rdata0_s<=16'b0;
	end
	// else if(psram_rd_val0_r) begin
	else if((psram_rd_sel&psram_rd_val0_r)|((!psram_rd_sel)&psram_rd_val0_get[3])) begin
		psram_rdata0_s<=psram_rdata0;
	end
end 


always @ (posedge psram_clk or negedge rstn) begin
	if (!rstn) begin
		psram_rd_val1_s<=1'b0;
	end
	else begin
		psram_rd_val1_s<=psram_rd_val1;
	end
end 

assign psram_rd_val1_r = psram_rd_val1&(!psram_rd_val1_s);

always @ (posedge psram_clk or negedge rstn) begin
	if (!rstn) begin
		psram_rdata1_s<=16'b0;
	end
	else if(psram_rd_val1_r) begin
		psram_rdata1_s<=psram_rdata1;
	end
end 



reg[15:0] psram_wdata_set;
reg psram_wdata_sel;



always @ (posedge psram_clk or negedge rstn) begin
	if (!rstn) begin
		psram_wdata_sel<=1'b0;
	end
	else 
		psram_wdata_sel<=psram_ctrl[4] ;
	
end 

always @ (posedge psram_clk or negedge rstn) begin
	if (!rstn) begin
		psram_wdata_set<=16'b0;
	end
	else if(psram_data_load0&(!psram_wdata_sel)) 
		psram_wdata_set<=psram_wdata_set+1;
	else
		psram_wdata_set<=psram_wdata[15:0];
	
end 
assign psram_wdata_o0=psram_wdata_set[15:0];
assign psram_wdata_o1=psram_wdata_set[15:0];

// assign psram_wdata_o0=psram_wdata[15:0];
// assign psram_wdata_o1=psram_wdata[15:0];

`else

//******************************************************************//

assign psram_wfifo_rstn=psram_ctrl[2]&rstn;
assign psram_rfifo_rstn=psram_ctrl[6]&rstn;	
//******************************************************************//

always @ (posedge pclk or negedge rstn) begin
	if (!rstn) begin
		psram_wfifo_en_f<=1'b0;
		psram_wfifo_en_s<=1'b0;
	end
	else begin
		psram_wfifo_en_f<=psram_ctrl[9];
		psram_wfifo_en_s<=psram_wfifo_en_f;
	end
end 

assign psram_wfifo_en=psram_wfifo_en_f&(!psram_wfifo_en_s);

always @ (posedge pclk or negedge rstn) begin
	if (!rstn) begin
		psram_rfifo_en_f<=1'b0;
		psram_rfifo_en_s<=1'b0;
	end
	else begin
		psram_rfifo_en_f<=psram_ctrl[10];
		psram_rfifo_en_s<=psram_rfifo_en_f;
	end
end 

assign psram_rfifo_en=psram_rfifo_en_f&(!psram_rfifo_en_s);

//******************************************************************//
//wr fifo

// fifo_psram_16bit fifo_psram_16bit0(
    // .wclk(pclk),
    // .rclk(psram_clk),
    // .rrst_n(psram_wfifo_rstn),
    // .wrst_n(psram_wfifo_rstn),
    // .wdata(psram_wdata[15:0]),
    // .rdata(psram_wdata_o0),
    // .wen(psram_wfifo_en),
    // .ren(psram_data_load0),
    // .rempty(),
    // .wfull()
// );

// fifo_psram_16bit fifo_psram_16bit1(
    // .wclk(pclk),
    // .rclk(psram_clk),
    // .rrst_n(psram_wfifo_rstn),
    // .wrst_n(psram_wfifo_rstn),
    // .wdata(psram_wdata[31:16]),
    // .rdata(psram_wdata_o1),
    // .wen(psram_wfifo_en),
    // .ren(psram_data_load0),
    // .rempty(),
    // .wfull()
// );

//******************************************************************//
//rd fifo

// fifo_psram_16bit fifo_psram_16bit2(
    // .wclk(psram_rd_clk),
    // .rclk(pclk),
    // .rrst_n(psram_rfifo_rstn),
    // .wrst_n(psram_rfifo_rstn),
    // .wdata(psram_rdata0[15:0]),
    // .rdata(psram_rdata0_d),
    // .wen(psram_rd_val0),
    // .ren(psram_rfifo_en),
    // .rempty(),
    // .wfull()
// );

// fifo_psram_16bit fifo_psram_16bit3(
    // .wclk(psram_rd_clk),
    // .rclk(pclk),
    // .rrst_n(psram_rfifo_rstn),
    // .wrst_n(psram_rfifo_rstn),
    // .wdata(psram_rdata1[31:16]),
    // .rdata(psram_rdata1_d),
    // .wen(psram_rd_val1),
    // .ren(psram_rfifo_en),
    // .rempty(),
    // .wfull()
// );

`endif

endmodule


















